A dynamic random access memory (DRAM) device is commonly used in electronic systems to store data. A typical DRAM device includes memory cells arranged in an array and peripheral circuit around the memory cell array, with each memory cell generally consisting of a capacitor coupled through a transistor gate electrode or wordline stack to a bit or digit line. The doped regions or active area of a transistor fabricated in a semiconductive substrate are typically contacted using polysilicon (poly) plugs, which may connect with a capacitor, a bit line, or other conductor layers.
In the formation of local interconnects in memory devices, it is difficult to form low resistance peripheral contacts while maintaining high quality array contacts.
In a conventional process flow for fabricating a DRAM device, contact openings are formed through insulative layers in the DRAM peripheral area to active areas in the substrate and in the DRAM array area poly plugs connected to diffusion regions, and filled with conductive material to form peripheral and array contacts. A problem faced in making a DRAM local interconnect contact is that there are subsequent temperature steps which make it difficult to put down chemical vapor deposited (CVD) films early in the DRAM fabrication process flow. Although films such as physical vapor deposited (PVD) TiN can withstand high process temperatures, they are high in resistivity, making them undesirable for forming contacts on a silicon substrate.
CVD titanium (CVD Ti) provides a desirable film for fabricating a low resistivity resistance contact. However, problems such as delamination of subsequently depositing film layers that are formed over a CVD Ti layer can develop. In addition, a CVD Ti layer deposited onto the amorphous silicon highly doped poly plugs exposed in the memory cell array result in the formation of titanium silicide (TiSix) in the poly plugs resulting in the development of voids within the plugs. Further, due to die shrinkage, there is a trend to fabricate DRAM wordlines (gate stacks) of tungsten rather than tungsten silicide, due to the lower resistivity of tungsten. However, in utilizing titanium to form interconnects to the tungsten layer of a gate stack, it is difficult to selectively remove portions of the titanium layer to form the gate contacts without adversely affecting the exposed tungsten of the stack.
It would be desirable to provide a process that overcomes such problems.